Semiconductor device packages or integrated circuit chip carriers find use in a variety of high-density electronics applications. The integrated circuits or semiconductor devices are typically protected from the external environment by encapsulation with an epoxy material (using glob top technology for example) or transfer molding a thermoset or thermoplastic resin about the device. This package provides protection from dust, humidity and other environmental factors which can destroy the delicate circuitry.
A major problem associated with these types of packages is that they do not provide shielding from radiation, such as radio frequency interference (RFI) or electromagnetic interference (EMI). The ability to shield high-frequency circuits, especially in electronic equipment such as two-way radios, is critical. Conventional shielding systems are generally characterized by a conductive metallic enclosure constructed to surround the device to be shielded. This enclosure acts either to protect the electrical equipment from external RFI or EMI signals or to prevent the escape of RFI or EMI signals generated by the device. Typically, these shielded enclosures are made from a conductive material that is electrically coupled to the surrounding area. In prior art, the shielded enclosures have been made by attaching a drawn metallic casing over the semiconductor device and soldering it to a substrate connected to the device.
Unfortunately, this method of shielding is extremely sensitive and very costly and cumbersome when used to shield integrated circuits because of 1) high temperatures generated during the soldering process for attaching the metal shield to the device and 2) the additional thickness or bulk required when adding a shield. Heat generated by the soldering process can result in damage to the integrated circuit. The increase in the overall size of the shielded package is substantial, resulting in a package that is larger than optimum. As a result, a need exists for a method to provide RFI shielding to a high-density integrated circuit package that is economical, does not generate excessive temperatures, and provides a low-profile, high-density package.
Erasable programmable read-only memory (hereinafter called EPROM) packages which can be erased by an ultra-violet (UV) light ray consist of an EPROM chip mounted on a substrate. In prior art plastic packages, the EPROM chip is encapsulated, and a window made of a material capable of transmitting UV (ultraviolet) light, such as UV transparent glass, quartz, alumina, or synthetic resin is securely fixed to the encapsulant with epoxy resin. This structure has such poor moisture resistance that water or corrosive ions, such as sodium, potassium, or chloride ions, penetrate the window through the portion at which the window and the encapsulant are joined, thereby causing corrosion or leakage between electrodes of the EPROM chip 14. Some packaging methods passivate the EPROM chip with a resin, typically a silicone resin, capable of transmitting UV light, filling the space above the chip. Conventional EPROM packages suffer from a number of disadvantages, such as:
(1) UV light permeable silicone resins have relatively low adhesive strength and high water permeability, hence the moisture resistance of the package is poor. Additionally, since the plastic package has relatively low resistance to thermal stress, the quality of the package is degraded by repeated thermal cycling. PA1 (2) The silicone resin used in the plastic package is rather expensive, and even though it provides sufficient UV transmittance, it would be desirable to eliminate it. PA1 (3) The difference in thermal expansion coefficients between the epoxy sealing resin, the base material, the cover, and the UV light permeable resin sometimes generates cracks in the UV light permeable resin. PA1 (4) Assembly requires substantial time. PA1 (5) The need to add a separate cover and UV window to the cover creates a finished assembly which is larger and taller than desired. A package with less wasted space in the horizontal and vertical directions would be desirable. PA1 1. Providing a substrate of insulating material with a metallization pattern on at least one side, and an EPROM chip mechanically and electrically attached to the metallization pattern; PA1 2. Encapsulating the EPROM chip and the metallization pattern in a resin that is at least partially transparent to UV light; PA1 3. Vacuum depositing an adherent metal coating that is at least partially transparent to UV light, over the resin and a portion of the substrate; and PA1 4. Coating the adherent metal coating with an adherent organic coating that is at least partially transparent to UV light.
Clearly, a need exists for an electromagnetically shielded package for an EPROM that overcomes the deficiencies of the prior art.